1. Field of the Invention
The present invention relates to a delay time compensation circuit, and more particularly to an improved delay time compensation circuit for a clock buffer which makes it possible to effectively compensate for the time delayed by a clock buffer.
2. Description of the Background Art
In general, a signal input terminal and a signal output terminal in a synchronous system become synchronized and activated based on an edge of an input clock signal. The input clock is required to pass through a clock buffer to drive an overloaded capacitance load in an internal system. Thus, the clock signal internally employed in a system and the clock signal at the output of that same system have a time delay in comparison to an input clock signal. Also, the faster becomes an operation speed of the synchronous system, the more difficult the synchronization due to the gradual increase of the time delay.
Conventional circuits have been designed in an attempt to obtain an output clock signal which is synchronized with an input clock signal by compensating for a delay time of the input clock signal caused by the clock buffer. For instance, conventional circuits include a phase-locked loop (PLL) circuit or a delay-locked loop (DLL) circuit which employs a feedback technique, and a negative-delay circuit (NDC) or a synchronous mirror delay (SMD) circuit which does not employ a feedback technique. The above-mentioned circuits are designed to internally generate clock signals that are ahead of the input clock signal by an amount of time that corresponds to the delay time introduced by the clock buffer, thus compensating for the delay time caused by the clock buffer in order to generate output clock signals which are synchronized to input clock signals.
FIG. 1 is a block diagram illustrating a DLL circuit which adopts such a feedback technique.
As shown therein, an input buffer FB1 has a delay time t.sub.B1, and an output buffer FB2 has a delay time t.sub.B2. The DLL circuit is designed to compensate for the respective delay times t.sub.B1, t.sub.B2 in accordance with the respective input and output buffers FB1, FB2. The DLL circuit includes a delay device VB having a variable delay time t.sub.D, a feedback delay device FB3 having a fixed delay time t.sub.F, and a phase detector 10.
Initially, an input clock signal ICLK (FIG. 3A) passes through the input buffer FB1 and is changed, after a period of t.sub.B1, into a clock signal RCLK (FIG. 3B). The phase detector 10 then compares respective phases of the clock signal RCLK and the clock signal FCLK (FIG. 3E), which is fed back, thereby generating a control signal CS which corresponds to the difference compared.
Next, the variable delay device VB delays the clock signal RCLK by the delay time t.sub.D, which is determined based on the control signal CS, thereby generating a clock signal DCLK (FIG. 3C). The clock signal DCLK becomes delayed in the output buffer FB2 by a time period of t.sub.B2, such that a final output clock signal OCLK is synchronized with the input clock signal ICLK, as shown in FIG. 3D.
The final output clock signal OCLK passes through the feedback delay device FB3 and becomes, after a time period of t.sub.F, the feedback clock signal FCLK (FIG. 3E).
The above-mentioned feedback circuit satisfies the following expression: EQU T.sub.CLK =t.sub.D +t.sub.B2 +t.sub.F.
Accordingly, the clock signals RCLK, FCLK become identical to each other in phase, and the output clock signal OCLK becomes synchronized with the input clock signal ICLK.
However, when the DLL circuit is employed, the delay device VB is initially set to an initial synchronous setting time that is proportional to a square value of a clock cycle T.sub.CLK, thereby elongating a delay time disadvantageously.
Also, in order to decrease power consumption, delay correction is suspended when an input clock signal ICLK is briefly interrupted in a standby state and started anew when a clock signal is restored to a normal state in which a clock signal is required. Thus, when a difference between the output clock signal and the input clock signal is significant, the amount of time required to achieve restoration from standby state to normal state is increased. In addition, there occurs a jittering phenomenon in which an edge start point of the output clock signal becomes changed.
The above disadvantage is attributable to the feedback technique applied to the DLL circuit. To avoid these disadvantages a circuit may be designed with an NDC which does not rely on a feedback to compensate for the delay times t.sub.B1, t.sub.B2 associated with the clock buffers FB1, FB2. Such a circuit is shown by FIG. 2.
That is, when an input clock signal ICLK (FIG. 4A) and a delay clock signal DCLK (FIG. 4B) are applied to NDC 20, a difference (T.sub.CLK.backslash.2-T.sub.DEL) is obtained between a half cycle T.sub.CLK.backslash.2 of the input clock ICLK and the delay time t.sub.DEL of the input buffer corresponding to the respective rising edges of the two clock signals. NDC 20 generates a clock signal NCLK (FIG. 4C) by delaying the falling edge of input clock signal ICLK by a timed delay equivalent to the difference (T.sub.CLK.backslash.2-t.sub.DEL), which difference represents the difference between the falling edge t1 of the input clock signal ICLK and the rising edge of the delay clock signal DCLK. Thus, the rising edge of the clock signal NCLK leads the rising edge of the input clock signal ICLK by a time period of t.sub.DEL, and an output clock signal OCLK (FIG. 4D) can be synchronized with the input clock signal ICLK after one period.
However, when using the NDC 20, data corresponding to both the rising and falling edges of an input clock signal ICLK is required. That is, the delay time t.sub.DEL corresponding to the input buffer FB1 is evaluated at a time point t1 which corresponds to the midpoint of input clock signal ICLK (T.sub.CLK.backslash.2) or the falling edge of the input clock signal ICLK. Therefore, the rising edge of the output signal NCLK is generated after a time period (T.sub.CLK.backslash.2-t.sub.DEL) from the time point tl. Also, because the half cycle value is used, the input clock signal ICLK must keep a precise duty cycle of 50% in addition to the rising edge.
The delay time t.sub.DEL in the clock buffer FB1 may be compensated using the above method when: EQU T.sub.CLK /2-N.times.Tstage.ltoreq.t.sub.DEL.ltoreq.T.sub.CLK /2 (1),
where Tstage denotes a delay time for a unit delay device within NDC 20, and N denotes the number of unit delay devices within NDC 20.
If an entire delay time (N.times.Tstage) for a delay device chain that is composed of the unit delay devices of NDC 20 remains within the half cycle (T.sub.CLK /2), the expression (1) may be changed as follows: EQU 0.ltoreq.t.sub.DEL.ltoreq.T.sub.CLK /2 (2).
From this expression, it should be understood that the delay time t.sub.DEL of the clock buffer must be less than a half cycle of the input clock signal ICLK to be compensated with the above-described system.
Therefore, if a magnitude of the clock buffer must be increased to activate a large capacitance load, the delay time of the clock buffer may not satisfy expression (2), rendering the above-described system incapable of computing for the delay time using NDC 20.
Also, since the pulse width of the output clock signal OCLK corresponds to the delay time t.sub.DEL of the clock buffer, the pulse width becomes variable in proportion to the variation of the delay time t.sub.DEL.